Type Members

1.  abstract class Apb2Bundle extends Bundle
2.  class Apb2CSTrgt extends Module

   Basic APB2 Control/Status register target generator with Control/Status register map supplied via a simple JSON description.

   Apb2CSTrgt

   Basic APB2 Control/Status register target generator with Control/Status register map supplied via a simple JSON description.

   The following register bit field types are supported:

   RW register bits

   Read-write. Generally these are static configuration bit fields and are connected to Outputs. The register bits can only be set or cleared by writing to the register.

   RO register bits

   Read-only. These are connected to Inputs which should be driven by registered external status signals from the design instantiating Apb2CSTrgt. Writing to these registers has no effect.

   WO register bits

   Write-only. These are connected to Outputs but after being written to '1' they are always set back to to '0' on the following clock cycle, so writing a '1' to a WO register bit will create a single-cycle pulse on the corresponding Output. This bit field mode can be used to implement 'go bits' which trigger some event elsewhere in the design instantiating Apb2CSTrgt. Writing a '0' has no effect, reads are always '0'.

   W1C register bits

   Write-1-to-clear. These are connected to Inputs on which a single cycle pulse will set the corresponding register bit to '1'. Writing a '1' to the same bit will clear it. Writing a '0' has no effect, regardless of the current value of the bit. This bit field mode is the one to use for interrupt status registers. Interrupt enable/mask registers should be implemented using RW bit fields with the enable/mask logic implemented externally in the design instantiating Apb2CSTrgt.

   To do

   implement pProt

   implement check that there are no spaces in register or regType names in JSON

   Note

   pStrb is implemented as follows: pStrb bits are used to mask or enable writes to individual bytes of bit fields. However, if a bit field straddles two or more byte lanes and not ALL the corresponding bits of pStrb are set then the bit field is not written (at all) and pSlvErr is signalled. In other words, partial writes to bitfields are not supported; either the whole bit field is written, when ALL corresponding pStrb bits are set, or the bit field is not written at all. Writing to a register with NONE of the pStrb bits corresponding to a given bit field set is OK and is NOT an error condition. This is a design decision. The AMBA APB2 spec only discusses the pStrb bits in the context of the validity of the byte lanes of the write data bus. The JSON register description specifies the width of each register type. All registers in a given JSON must have width >= DATA_W and if width is > DATA_W then it must be power of two a multiple of DATA_W. i.e. 64 bit registers are supported with 32 bit access but 96 bit registers are not supported and 16 bit registers are not supported with 32 bit access, for example. If a register wider than DATA_W specifies a field which straddles the DATA_W boundary then it is broken into two (or more) pieces, for DATA_W access, which are concatenated together.

3.  class Apb2IO extends Apb2Bundle
4.  class Apb2Net extends Module

   Parameterizable number of initiators and memory mapped targets.

   APB2 Network

   Parameterizable number of initiators and memory mapped targets. Arbitration between initiators for access to targets. Default parameterization connects one APB initiator to two APB targets. Cross-bar network topology. To be clear, this Module drives its targets and responds to its initiators, but where it is instantiated its initators are targets and its targets are initiators.

   To do

   implement PIPE_CTRL as described

   Note

   targets are assumed to be contiguously mapped from the base (with no gaps in map, i.e. if there are two targets of size 4kB and 8kB, respectively, and the base address of the first is @0x0 then the base address of the second is implicitly @4kB)

   ,

   this module is not optimized for throughput, but for easy timing closure and low power

5.  class Apb2RegFile extends Module

   APB2 target implementing bank of 4x 32 bit (by default) read/write registers

   Apb2RegFile

   APB2 target implementing bank of 4x 32 bit (by default) read/write registers

6.  class Apb2Req extends Apb2Bundle

   Direction of AMBA APB2 IOs are from target perspective (i.e.

   AMBA APB2 IO Bundle

   Direction of AMBA APB2 IOs are from target perspective (i.e. request = Input, response = Output)

7.  class Apb2ReqCtrl extends Apb2Bundle

   Apb2ReqCtrl is the same as Apb2Req Bundle but without pSel.

   Apb2ReqCtrl Bundle

   Apb2ReqCtrl is the same as Apb2Req Bundle but without pSel. This Bundle is used below in DecoupledIO where the pSel signal from Apb2Req Bundle is used to drive valid.

8.  class Apb2Rsp extends Apb2Bundle
9.  class Apb2Slice extends Module

   APB2 bus register slice for pipelining/timing closure.

   APB2 Slice

   APB2 bus register slice for pipelining/timing closure.

10.  class ExampleApb2CSTrgt extends Module

    Example wrapper for Apb2CSTrgt Module, parameterized with src/main/json/Example.json which connects the MixedVec IO on the parameterized Module to IO using pre-generated and auto-generated Bundles from src/main/scala/examples/Example.scala

    ExampleApb2CSTrgt

    Example wrapper for Apb2CSTrgt Module, parameterized with src/main/json/Example.json which connects the MixedVec IO on the parameterized Module to IO using pre-generated and auto-generated Bundles from src/main/scala/examples/Example.scala

11.  class _ExampleRoVec_ extends Bundle
12.  class _ExampleRwVec_ extends Bundle

    THIS IS AUTO-GENERATED CODE - DO NOT MODIFY BY HAND!

    Bundles for Connection to Apb2CSTrgt(REG_DESC_JSON

    THIS IS AUTO-GENERATED CODE - DO NOT MODIFY BY HAND!

13.  class _ExampleWcVec_ extends Bundle
14.  class _ExampleWoVec_ extends Bundle