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  Definition Classes

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•  package ambel

  Definition Classes

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•  class Apb2CSTrgt extends Module

  Basic APB2 Control/Status register target generator with Control/Status register map supplied via a simple JSON description.

  Apb2CSTrgt

  Basic APB2 Control/Status register target generator with Control/Status register map supplied via a simple JSON description.

  The following register bit field types are supported:

  RW register bits

  Read-write. Generally these are static configuration bit fields and are connected to Outputs. The register bits can only be set or cleared by writing to the register.

  RO register bits

  Read-only. These are connected to Inputs which should be driven by registered external status signals from the design instantiating Apb2CSTrgt. Writing to these registers has no effect.

  WO register bits

  Write-only. These are connected to Outputs but after being written to '1' they are always set back to to '0' on the following clock cycle, so writing a '1' to a WO register bit will create a single-cycle pulse on the corresponding Output. This bit field mode can be used to implement 'go bits' which trigger some event elsewhere in the design instantiating Apb2CSTrgt. Writing a '0' has no effect, reads are always '0'.

  W1C register bits

  Write-1-to-clear. These are connected to Inputs on which a single cycle pulse will set the corresponding register bit to '1'. Writing a '1' to the same bit will clear it. Writing a '0' has no effect, regardless of the current value of the bit. This bit field mode is the one to use for interrupt status registers. Interrupt enable/mask registers should be implemented using RW bit fields with the enable/mask logic implemented externally in the design instantiating Apb2CSTrgt.

  Definition Classes

  ambel

  To do

  implement pProt

  implement check that there are no spaces in register or regType names in JSON

  Note

  pStrb is implemented as follows: pStrb bits are used to mask or enable writes to individual bytes of bit fields. However, if a bit field straddles two or more byte lanes and not ALL the corresponding bits of pStrb are set then the bit field is not written (at all) and pSlvErr is signalled. In other words, partial writes to bitfields are not supported; either the whole bit field is written, when ALL corresponding pStrb bits are set, or the bit field is not written at all. Writing to a register with NONE of the pStrb bits corresponding to a given bit field set is OK and is NOT an error condition. This is a design decision. The AMBA APB2 spec only discusses the pStrb bits in the context of the validity of the byte lanes of the write data bus. The JSON register description specifies the width of each register type. All registers in a given JSON must have width >= DATA_W and if width is > DATA_W then it must be power of two a multiple of DATA_W. i.e. 64 bit registers are supported with 32 bit access but 96 bit registers are not supported and 16 bit registers are not supported with 32 bit access, for example. If a register wider than DATA_W specifies a field which straddles the DATA_W boundary then it is broken into two (or more) pieces, for DATA_W access, which are concatenated together.

• BitField
• BitFieldDetails
• Register
• RegisterAttr
• RegisterBits
• RegisterDesc
• RegisterDescDecoder
• RegisterType

ambel.Apb2CSTrgt

RegisterDescDecoder 