c

ambel

Apb2CSTrgt

class Apb2CSTrgt extends Module

Apb2CSTrgt

Basic APB2 Control/Status register target generator with Control/Status register map supplied via a simple JSON description.

The following register bit field types are supported:

RW register bits

Read-write. Generally these are static configuration bit fields and are connected to Outputs. The register bits can only be set or cleared by writing to the register.

RO register bits

Read-only. These are connected to Inputs which should be driven by registered external status signals from the design instantiating Apb2CSTrgt. Writing to these registers has no effect.

WO register bits

Write-only. These are connected to Outputs but after being written to '1' they are always set back to to '0' on the following clock cycle, so writing a '1' to a WO register bit will create a single-cycle pulse on the corresponding Output. This bit field mode can be used to implement 'go bits' which trigger some event elsewhere in the design instantiating Apb2CSTrgt. Writing a '0' has no effect, reads are always '0'.

W1C register bits

Write-1-to-clear. These are connected to Inputs on which a single cycle pulse will set the corresponding register bit to '1'. Writing a '1' to the same bit will clear it. Writing a '0' has no effect, regardless of the current value of the bit. This bit field mode is the one to use for interrupt status registers. Interrupt enable/mask registers should be implemented using RW bit fields with the enable/mask logic implemented externally in the design instantiating Apb2CSTrgt.

To do

implement pProt

implement check that there are no spaces in register or regType names in JSON

Note

pStrb is implemented as follows: pStrb bits are used to mask or enable writes to individual bytes of bit fields. However, if a bit field straddles two or more byte lanes and not ALL the corresponding bits of pStrb are set then the bit field is not written (at all) and pSlvErr is signalled. In other words, partial writes to bitfields are not supported; either the whole bit field is written, when ALL corresponding pStrb bits are set, or the bit field is not written at all. Writing to a register with NONE of the pStrb bits corresponding to a given bit field set is OK and is NOT an error condition. This is a design decision. The AMBA APB2 spec only discusses the pStrb bits in the context of the validity of the byte lanes of the write data bus. The JSON register description specifies the width of each register type. All registers in a given JSON must have width >= DATA_W and if width is > DATA_W then it must be power of two a multiple of DATA_W. i.e. 64 bit registers are supported with 32 bit access but 96 bit registers are not supported and 16 bit registers are not supported with 32 bit access, for example. If a register wider than DATA_W specifies a field which straddles the DATA_W boundary then it is broken into two (or more) pieces, for DATA_W access, which are concatenated together.

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  1. Apb2CSTrgt
  2. Module
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  5. IsInstantiable
  6. HasId
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Instance Constructors

  1. new Apb2CSTrgt(DATA_W: Int = 32, REG_DESC_JSON: String, VERBOSE: Boolean = false, GEN_BUNDLE: Boolean = false)

    DATA_W

    the width of the APB2 data bus in bits

    REG_DESC_JSON

    a string giving the path to the register description JSON to be generated

    VERBOSE

    enables verbose output during generation

    GEN_BUNDLE

    enables generation of Scala Bundles suitable for connection to the generated MixedVec IOs. The signal names used in the Bundles match their corresponding register and bit field names, as specified in the JSON. They are declared in the same order as the entries of the corresponding MixedVecs and are therefore very simple to connect to create wrapper Modules with named IO for specific (JSON) parameterizations of Apb2CSTrgt

Type Members

  1. case class BitField(bits: List[Int], name: String, mode: Option[String], resetVal: Option[Int], comment: Option[String]) extends Product with Serializable
  2. case class BitFieldDetails(reg: UInt, pos: Int, width: Int, mode: String, name: String) extends Product with Serializable
  3. case class Register(offset: Int, name: String, typeRef: String, comment: Option[String]) extends Product with Serializable
  4. case class RegisterAttr(offset: Int, width: Int, typeRef: String) extends Product with Serializable
  5. case class RegisterBits(name: String, fields: List[BitField]) extends Product with Serializable
  6. case class RegisterDesc(regMap: List[Register], regTypes: List[RegisterType]) extends Product with Serializable
  7. case class RegisterType(typeRef: String, width: Int, fields: List[BitField], comment: Option[String]) extends Product with Serializable

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. val ADDR_W: Int
  5. def IO[T <: Data](iodef: T): T
    Attributes
    protected
    Definition Classes
    BaseModule
  6. val MAX_REGS: Int
  7. val NUM_BITS_SHIFT: Int
  8. val NUM_BYTE: Int
  9. val NUM_REGS: Int
  10. def _bindIoInPlace(iodef: Data): Unit
    Attributes
    protected
    Definition Classes
    BaseModule
  11. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  12. def _compatAutoWrapPorts(): Unit
    Definition Classes
    BaseModule
  13. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  14. val attributes: List[RegisterAttr]
  15. val bundlePrefix: String
  16. var bytes: Int
  17. val chisel3BundleFileName: String
  18. val chisel3BundleFilePath: String
  19. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  20. final val clock: Clock
    Definition Classes
    Module
  21. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
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    Annotations
    @throws( ... ) @native() @HotSpotIntrinsicCandidate()
  22. val compileOptions: CompileOptions
    Definition Classes
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  23. def desiredName: String
    Definition Classes
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  24. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  25. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  26. val fields: List[List[BitField]]
  27. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  28. def getCommands: Seq[Command]
    Attributes
    protected
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  29. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
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  30. def hasSeed: Boolean
    Definition Classes
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  31. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  32. def instanceName: String
    Definition Classes
    BaseModule → HasId → InstanceId
  33. val io: Bundle { ... /* 5 definitions in type refinement */ }
  34. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  35. val jsonString: String
  36. final lazy val name: String
    Definition Classes
    BaseModule
  37. def nameIds(rootClass: Class[_]): HashMap[HasId, String]
    Attributes
    protected
    Definition Classes
    BaseModule
  38. val names: List[String]
  39. val namesAndBits: List[RegisterBits]
  40. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  41. final def notify(): Unit
    Definition Classes
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    Annotations
    @native() @HotSpotIntrinsicCandidate()
  42. final def notifyAll(): Unit
    Definition Classes
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    @native() @HotSpotIntrinsicCandidate()
  43. val offNameMap: Map[Int, String]
  44. val offsets: List[Int]
  45. val pAddrFF: UInt
  46. val pRDataFF: UInt
  47. val pReadyFF: Bool
  48. val pSlvErrFF: Bool
  49. val pWriteFF: Bool
  50. def parentModName: String
    Definition Classes
    HasId → InstanceId
  51. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  52. def pathName: String
    Definition Classes
    HasId → InstanceId
  53. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  54. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  55. def prettyPrintBitField(f: BitField): Unit
  56. def prettyPrintReg(r: Register): Unit
  57. def prettyPrintRegType(t: RegisterType): Unit
  58. def printRegMap(m: RegisterDesc): Unit
  59. val regArr: Array[ArrayBuffer[BitFieldDetails]]
  60. val regDesc: Option[RegisterDesc]
  61. val regIndex: UInt
  62. val regMap: Map[String, RegisterAttr]
  63. final val reset: Reset
    Definition Classes
    Module
  64. val roBundleBuffer: ListBuffer[String]
  65. val roIt: Iterator[UInt]
  66. var roRegBits: ListMap[String, Int]
  67. val rwBundleBuffer: ListBuffer[String]
  68. val rwIt: Iterator[UInt]
  69. var rwRegBits: ListMap[String, Int]
  70. val sorted: List[RegisterAttr]
  71. def suggestName(seed: ⇒ String): Apb2CSTrgt.this.type
    Definition Classes
    HasId
  72. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  73. final def toAbsoluteTarget: IsModule
    Definition Classes
    BaseModule → InstanceId
  74. def toCamelCase(s: String): String
  75. final def toNamed: ModuleName
    Definition Classes
    BaseModule → InstanceId
  76. def toString(): String
    Definition Classes
    AnyRef → Any
  77. final def toTarget: ModuleTarget
    Definition Classes
    BaseModule → InstanceId
  78. val typeFieldMap: Map[String, List[BitField]]
  79. val typeWidthMap: Map[String, Int]
  80. val types: List[String]
  81. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  82. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
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    @throws( ... ) @native()
  83. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  84. val wcBundleBuffer: ListBuffer[String]
  85. val wcIt: Iterator[UInt]
  86. var wcRegBits: ListMap[String, Int]
  87. val widths: List[Int]
  88. val woBundleBuffer: ListBuffer[String]
  89. val woIt: Iterator[UInt]
  90. var woRegBits: ListMap[String, Int]
  91. def writeBundleMember(f: BitFieldDetails): String
  92. object RegisterDescDecoder

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
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    Annotations
    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated
  2. lazy val getPorts: Seq[Port]
    Definition Classes
    RawModule
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use DataMirror.modulePorts instead. this API will be removed in Chisel 3.6

  3. def override_clock: Option[Clock]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  4. def override_clock_=(rhs: Option[Clock]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  5. def override_reset: Option[Bool]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  6. def override_reset_=(rhs: Option[Bool]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

Inherited from Module

Inherited from RawModule

Inherited from BaseModule

Inherited from IsInstantiable

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

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